FFT Circuitry for a 4G Age

Centar LLC is a provider of fast Fourier transform (FFT) intellectual property (IP) for use in FPGA and ASIC-based embedded applications. It has developed a novel parallel matrix-based formulation of the discreet Fourier transform (DFT), which decomposes it into structured sets of b-point discreet Fourier transforms. All FFT circuits are constructed from synchronous, fine-grained, locally connected, regular arrays of small processing elements (PEs), consisting of a few registers, some multiplexors and an arithmetic element. Salient features of this technology are:

• Speed: The only FPGA FFT circuits with clock rates >500MHz using 65nm technology (e.g., Intel Stratix III).
• Throughput: Data rates as high as ~10G complex samples per second
• Dynamic Range: Combined block floating point and floating point architecture means smaller word lengths can be used for post processing operations such as equalization.
• Programmability: Easy customization of FFT properties, functionality and I/O interface.
• Non-powers-of-two transform sizes: A single ROM memory can store control parameters to support any number or size FFTs
• Scalability: Faster transforms can be implemented without architectural changes by increasing the array size along one dimension or duplicating the array structure
• Power: Interconnects are entirely local, reducing parasitic routing capacitances to keep power dissipation low and speed high
• Cyclic Prefix: Circuit architecture is designed to support any prefix value (most FFT circuits require additional circuits to perform this function
• Floating-Point (NEW):  IEEE754 single precision floating-point, fixed-size Stratix streaming circuits use far less of the FPGA fabric (1024-point FFT uses half the number of ALMs compared to the Intel's equivalent).  Also, Centar's new Arria 10 circuits run at a 571 MHz sampling rate and, with hardwired floating-point DSPs, only use 2234 ALMs for an entire 1024-point transform!

Products

• Power-of-two FFT: Fixed and variable (run-time selectable) size, 16 to 16,384 points.

• Non-power-of-two FFT: The reachable transform sizes for this class of designs are those that can be factored into a composite form based on small integers up to sizes of ~10. For example, the SC-FDMA LTE requirements would use the integers {2,3,5} to compute all 35 transform sizes, e.g., N=2ⁿ3^m5^q, where n,m, and q are integers. These can be fixed-size or variable and selectable at run-time.

Design	FPGA	LUT	Registers	Block RAM (9/18K)	Fmax	RB Average Throughput (cycles)	Throughput (Normalized)
Centar	Virtex-6	2915	2581	19	401	16.6N	1
Xilinx	Virtex-6	3849	4326	10	407	23.4N	0.72
Centar	Stratix III	3816	3188	29	400	16.6N	1
Intel	Stratix III	2600	N.A.	17	260	32.9N	0.31

Example: LTE SC-FDMA relative performance, average over 35 different DFT sizes. (For details click here.)

Tools

Because there are always a large number of (parallel) circuit architectures that can be obtained from an algorithm specification, Centar has developed an automated CAD tool, Symbolic Parallel Algorithm Development Environment (SPADE), to make the best choices. SPADE is the only such tool in existence that can find latency optimal circuits.