References

(1) Modified Faddeeva Algorithm for Concurrent Execution of Linear Algebraic Operations, Nash, J.G.and Hansen, S.,  IEEE Trans. Computers, Feb.1988, pp.129. (Basic theory of the Faddeev algorithm including discussion of generic applicatons.)

(2) Automatic Generation of Systolic Array Designs For Reconfigurable Computing, 2002 Int. Conf. Engineering of Reconfigurable Systems and Algorithms, Nash, J. Greg, "(ERSA 02), pp.176-182, June 2002.  (Expanded paper discussion of Faddeev architecture design with other examples.)

(3) Automatic Generation of Systolic Array Designs For Reconfigurable Computing, Presented at Engineering of Reconfigurable Systems and Algorithms (ERSA2002), International Multiconference in Computer Science, Las Vegas, NV, June 24-27, 2002.  (More pictorial views of architecture designs via presentation viewgraphs.)

(4) Automatic Generation of Systolic Array Designs For Reconfigurable Computing, (Paper with more Faddeev mapping details than (2) above.)