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Background Information and References
Publications (pdf):
- A New Class of High Performance FFTs (Proceedings IEEE Conference on Acoustics, Speech and Signal Processing, Honolulu, Hawaii, April 15-20, 2007)
- A High Performance Scalable FFT (Proceedings IEEE Wireless Communications & Networking Conference, Hong Kong, March 11-15, 2007)
- A High Performance Block Floating Point Systolic FFT Not Limited to Powers of Two (Proceedings GSPx 2006, Santa Clara, California)
- Computationally Efficient Systolic Array for Computing the Discreet Fourier Transform, IEEE Trans. Signal Processing, Vol. 53, No.12, December 2005, pp.4640-4641.
- LU Decomposition (Find lower triangular matrix, L, and upper triangular matrix, U, such that LU=A.)
- Automatic Generation of Systolic Array Designs For Reconfigurable Computing (Proceedings Engineering of Reconfigurable Systems and Algorithms (ERSA2002), International Multiconference in Computer Science, June, 2002. Overview of SPADE using mapping of the Faddeev algorithm- find CX+D, given AX=B, where A, B, C, and D are matrices-as an example. Viewgraphs below.)
- Constraint Directed CAD Tool For Automatic Latency-Optimal Implementation of 1-D and 2-D Fourier Transforms (Proceedings SPIE ITcom, July 2002. Focuses on how constraints can be used to define systolic architectures using LU decomposition, the matrix Lyapunov algorithm, and the discreet Fourier transform as examples. Viewgraphs below.)
- Hardware Efficient Base-4 Systolic Architecture for Computing the Discreet Fourier Transform (Proceedings IEEE Workshop on Signal Processing Systems, SIPS2002, October 2002. Describes a new technique for systolic calculation of the 1-D Fourier transform that reduces the number of complex multipliers needed by a factor of 4. Viewgraphs below.)
- ASIC/FPGA CAD Tool for Automated Systolic Algorithm Mapping, (Description of SPADE's use for mapping the Lyapunov matrix equation (find X given AX+XB=C).:
Presentations (ppt):
- A New Class of High Performance FFTs, (Presented at Seventh Annual Workshop on High Performance Embedded Computing, MIT Lincoln Laboratory, 21-23 Sept. 2006.)
- CAD Tool For Automatic Latency-Optimal Implementation of FPGA-based Systolic Arrays (Presented at the 10th ACM International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 24-26th, 2002.)
- Automatic Latency-Optimal Design of FPGA-based Systolic Arrays (Presented at the 10th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, April 21-24, 2002.)
- Automatic Generation of Systolic Array Designs For Reconfigurable Computing (Presented at Engineering of Reconfigurable Systems and Algorithms (ERSA2002), International Multiconference in Computer Science, Las Vegas, NV, June 24-27, 2002.)
- Constraint Directed CAD Tool For Automatic Latency-Optimal Implementation of 1-D and 2-D Fourier Transforms (Presented at SPIE ITcom 2002, Boston, MA, July 30, 2002.)
- Hardware Efficient Base-4 Systolic Architecture for Computing the Discreet Fourier Transform (Presented at IEEE Workshop on Signal Processing Systems (SIPS) San Diego, CA, October 2002.)
- High-Performance Scalable Base-4 Fast Fourier Transform Mapping, (Presented at Seventh Annual Workshop on High Performance Embedded Computing, MIT Lincoln Laboratory, 23-25 Sept. 2003).