Dr. J. Greg Nash
Curriculum Vitae
Education
UCLA
Electrical Engineering
MS 1970
UCLA
Electrical Engineering
Ph. D 1974
UCLA (Post-Doctoral)
Employment
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Centar,
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Hughes Research Labs,
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6/92-6/93, Laboratory Chief Scientist
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6/84-5/92, Head of the Information Processing and Computer Architecture Department
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9/75-5/84, Member of the Technical Staff and Senior Staff Scientist
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Experience
Dr. Greg Nash has
38 years of experience working in the areas of parallel algorithm
design, signal and image processing algorithms, systolic arrays,
parallel computing architectures, system design, ASIC design,
computer arithmetic, semiconductor devices and device physics. He
has over 70 technical publications, primarily dealing with signal
processing algorithms, architectures, tools and systems and has 10
issued patents.
From 1996-2002 at
Centar he successfully lead the development team that created the
Symbolic Parallel Algorithm Development Environment (SPADE) tool.
This is the only tool in existence that allows a designer to
easily and rapidly explore the design space of latency-optimal
parallel signal processing circuit implementations.
Presently he has an NSF contract to develop a specialized FFT
for wireless applications.
At Hughes Research
Labs he received two best paper awards in 1988 and 1991 and he
received the Hughes Group Patent award at Hughes Research Labs in
1989. He developed the Systolic/Cellular Processor for
use in airborne radar systems.
It contained a 16x16 array of custom 32-bit ASICs which he
designed, and was built to support efficient computation of
algorithms from FFTs to complex linear algebraic operations.
The system was delivered to the
Finally, he has
been active professionally, serving as Chairman of the IEEE VLSI
Signal Processing Committee from 1986 to 1988 and editor of the J.
of VLSI Signal Processing and has been on the organizational
committees of 10 signal/image processing workshops.